The present invention relates to a deep via construction for an integrated circuit semiconductor device, such as a chip, and to a method of manufacturing such a construction.
Deep vias, for example those greater than 5 μm, that are filled with metals such as, for example, copper, aluminium and tungsten, can experience thermal problems. This is especially the case in through-Si-vias that are used in three-dimensional chip stacking applications, which can be more than 100 μm in depth. Copper, for example, has a coefficient of thermal expansion (CTE) of around 16 ppm/° C. This means that a typical 50 μm deep copper filled via will expand in length by approximately 300 nm when it is heated from room temperature to 400° C, which is an example of a temperature reached during wafer processing, for example in chemical vapour deposition (CVD) or final annealing in back-end-of line (BEOL) processes. In other applications, the via depth can vary from 5 μm up to 300 μm, resulting in a thermal expansion of the via between 30 nm and 1800 nm. Should such expansion occur, then the materials closely surrounding the deep via, especially those films and the like located or deposited above the deep via, will be subject to severe stress that may lead to cracks and to film delamination.
Deep vias are formed in dielectric layers and comprise a dielectric cladding in contact with a substrate such as a silicon substrate and a metal fill in contact with the dielectric cladding. A contact area electrically connects the metal fill to interconnect wiring. Conventionally, the contact area is located above the upper surface of the metal fill of the deep via. The construction of conventional deep vias is such that should thermal expansion occur in the metal fill, dielectric and or metal layers located above the vias are subjected to considerable stress forces that may result in the formation of cracks.